List of Messages |
reg [3:0] sel; // sel is a onehot encoded signal reg result, a, b, c, d; always @ (sel or a or b or c or d) begin case(sel) // synthesis full_case 4'b0001: result = a; 4'b0010: result = b; 4'b0100: result = c; 4'b1000: result = d; endcase endThe example makes the assumption that sel is a onehot encoded variable.
ACTION: If your case statement does not require a default case item (that is, if there is a case item that matches every possible value of the case expression), add a full_case attribute to the case statement and/or remove the default case item, if it exists. If your case statement requires a default case item, do not add a full_case attribute to your case statement. Adding the attribute would cause a mismatch between the simulated behavior of the design and the synthesized netlist.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.