List of Messages |
CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you used the specified multidimensional array. Because the EDA Netlist Writer cannot regroup the multidimensional array into its bus, output file generation may result in a degenerate bus. However, logic synthesis is not affected.
ACTION: To avoid receiving this message in the future, edit the design to use a one- or two-dimensional array. Otherwise, no action is required.
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