| List of Messages | |
CAUSE: The specified nodes are registers that use asynchronous load and data signals to implement a latch. These nodes will be treated as latches during timing analysis, using the asynchronous load as the latch enable, and the asynchronous data as the data input for the latch. For more information, refer to the submessages.
ACTION: No action is required. However, the TimeQuest Timing Analyzer may not correctly analyze designs containing latches. Therefore, Altera recommends changing your design to remove the latches whenever possible. For more information, run the check_timing tcl command in the TimeQuest analyzer.
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