| List of Messages | |
CAUSE: Quartus Prime incremental compilation will not synthesize the specified design partition because there were no relevant design changes that would normally trigger Analysis & Synthesis. Be aware that changes to assignments other than device family do not trigger Analysis & Synthesis by design. You must manually set your netlist type to Source File if you change any assignments that impact Analysis & Synthesis and want those changes to impact this design partition.
ACTION: No action is required.
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