List of Messages
Parent topic: List of Messages

ID:12086 Created PLL "<name>" from CLKLOCKx1 Input Frequency logic option on input pin "<name>"

CAUSE: You set the CLKLOCKx1 Input Frequency logic option for the specified input pin. Turning this option on is equivalent to instantiating an altclklock megafunction with either of its ClockBoost parameters set to a value of 1.

ACTION: No action is required.

Parent topic: List of Messages

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.