List of Messages
Parent topic: List of Messages

ID:236033 If two bottom-up modules are allocated an overlapping portion of the chip, each may independently claim some common resources in this region. This overlap leads to resource conflicts when importing results into the final design. In general overlapping LogicLock regions may reduce quality of results.

CAUSE:

ACTION:

Parent topic: List of Messages

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.