List of Messages |
CAUSE: You specified a set of registers in an HDL design file that acts as RAM and you set the ramstyle attribute to MLAB. However, Analysis & Synthesis cannot implement the registers with MLAB because a mixed-width or byte-enabled RAM implementation is required. These features are not supported by MLAB inference.
ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, change the ramstyle attribute of the RAM logic to a value different from MLAB, use the same widths for write and read, or remove the byte-enable signals that control the write.
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