List of Messages |
CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. In addition to that, you turned off the Add Pass-Through Logic to Inferred RAMs logic option for the set of registers. Analysis & Synthesis then converted the registers into an altsyncram or altdpram megafunction to implement the register logic with a memory block on the target device. However, Analysis & Synthesis did not add an extra logic to guarantee that the read-during-write behavior of the RAM hardware matches the read-during-write behavior of the original design.
ACTION: If you want Analysis & Synthesis to add the extra logic, turn on the Add Pass-Through Logic to Inferred RAMs logic option. Otherwise, no action is required.
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