ID:186116 coreclk input ports (phase compensation FIFO read clock) of the following GXB receiver channels are sourced by the following signals and need to be the same frequency as the write clock of the receiver's phase compensation FIFO

CAUSE: The coreclk input port of the specified gigabit transceiver block (GXB) receiver channels are sourced by the specified signals other than the coreclk_out output signal of the gigabit transceiver block (GXB) transmitter PLL associated with this GXB receiver channel. The submessage(s) of this message list the GXB receiver channels and the signals that source them.

ACTION: Make sure that the signals are the same frequency as the write clock of the receiver phase compensation FIFOs.