List of Messages
Parent topic: List of Messages

ID:186020 Data bit position <number> of <number> bit wide data bus is missing a synchronization register in the core

CAUSE: The specified bit of a data bus is not synchronized to the core clock.

ACTION: Modify the design to synchronize all outputs of the SERDES receiver to the core clock.

Parent topic: List of Messages

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.