List of Messages |
CAUSE: You either used the altdqs megafunction or assigned the DQS Phase Shift and DQS Frequency logic option settings to the DQS I/O pin. The DQS phase shift is generated by the internal dedicated DDR I/O circuitry. On system power-up, the Fitter takes up to 256 clock cycles to align the system clock and the DDR I/O circuitry correctly with the specified DQS Phase Shift setting.
ACTION: No action is required. Be sure to wait until after the first 256 clock cycles at system power-up to send DQ I/O data to the device so that the DQS phase shift is correct.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.