ID:186313 Device takes up to 256 clock cycles to train dedicated DDR I/O circuitry to generate correct DQS phase shift on system power-up

CAUSE: You either used the altdqs megafunction or assigned the DQS Phase Shift and DQS Frequency logic option settings to the DQS I/O pin. The DQS phase shift is generated by the internal dedicated DDR I/O circuitry. On system power-up, the Fitter takes up to 256 clock cycles to align the system clock and the DDR I/O circuitry correctly with the specified DQS Phase Shift setting.

ACTION: No action is required. Be sure to wait until after the first 256 clock cycles at system power-up to send DQ I/O data to the device so that the DQS phase shift is correct.