| List of Messages | |
CAUSE: The gigabit transceiver block (GXB) PLL is successfully optimized and placed in the logical PLL location shown. As a result, fewer device resources are now required for this design.
ACTION: No action is required. This is a submessage of the message that precedes it in the Messages window.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.