List of Messages |
CAUSE: You specified even counter mode or value control for the PLL clock output (that is, either the CLK_USE_EVEN_COUNTER_MODE parameter is set to ON or the CLK_USE_EVEN_COUNTER_VALUE parameter is set to ON); however, specifying an even mode or value control forces the corresponding counter to use only even mode or have only an even value. This setting can make it difficult to achieve the requested duty cycle because it does not allow odd mode or odd counter values. This message is a submessage of the message that precedes it in the Messages window and in the Messages section of the Report window.
ACTION: No action is required.
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