List of Messages |
CAUSE: Some of the input clock nodes for the specified Clock Control Block are not using legal port connections. The inclk[0] and inclk[1] ports can only be driven by the dedicated clock pins, while inclk[2] and inclk[3] ports can only be driven by PLL counter output ports. The Compiler automatically changed the inputs so that they connect to legal ports, and adjusted the corresponding clkselect[] port connections to preserve the design functionality; however, the design may still not be processed successfully by the Fitter if the inputs to inclk[] ports are not placed correctly.
ACTION: No action is required. To avoid receiving this message in the future, modify the design and change the inclk ports to ensure that the ports are connected legally.
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