List of Messages |
CAUSE: In a Subprogram Declaration at the specified location in a VHDL Design File (.vhd), you used the specified mode for a formal parameter. However, the formal parameter must have a mode of IN, INOUT, or OUT.
ACTION: Change the mode of the formal parameter to IN, INOUT, or OUT.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.