List of Messages |
CAUSE: In a Subprogram Call at the specified location in a VHDL Design File (.vhd), you specified an actual for the specified formal parameter. However, the actual does not have the same specified object class or type (that is, signal, variable, constant, or file) as the formal parameter. The object class or type of the actual must match the object class or type of the formal.
ACTION: Change the object class/type of the actual to match the formal, or change the object class/type of the formal to match the actual.
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