List of Messages |
CAUSE: In an Interface Declaration at the specified location in a VHDL design file (.vhd), you declared the specified interface object with a mode of Out. Integrated Synthesis attempted to read the value of the interface object, but cannot do so because the interface object has the mode Out.
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY example IS PORT ( ena : IN BIT; i : IN BIT; o : OUT BIT ); END example; ARCHITECTURE a OF example IS SIGNAL tmp : BIT; BEGIN PROCESS (ena, i) BEGIN CASE ena IS WHEN '1' => tmp <= i; WHEN OTHERS => tmp <= tmp; END CASE; END PROCESS; o <= tmp; END a;
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