List of Messages |
CAUSE: In a Process Statement at the specified location in a VHDL Design File (.vhd), you used both a sensitivity list and a Wait Statement. However, because the sensitivity list acts as an implicit Wait Statement, the Process Statement cannot contain both a sensitivity list and a Wait Statement.
ACTION: Remove either the sensitivity list or the Wait Statement from the Process Statement.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.