List of Messages |
CAUSE: You used a matching case statement in your VHDL design file. However, the type of the case expression you used is not supported for a matching case statement.The case expression of a matching case statement must be of type 'bit' or 'std_ulogic', or a one-dimensional array of type 'bit' or 'std_ulogic'.
ACTION: Use a supported case expression type in a matching case statement, or use an ordinary case statement with the given type.
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