List of Messages |
CAUSE: In a VHDL Design File (.vhd) at the specified location, you used an Exit Statement. However, you did not use the Exit Statement in the Loop Statement for the specified loop. The Exit Statement must be inside the Loop Statement.
ACTION: Move the Exit Statement inside the Loop Statement, or expand the Loop Statement so it includes the Exit Statement.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.