List of Messages |
CAUSE: In a Binding Indication at the specified location in a VHDL Design File (.vhd), you associated a component with a design entity. However, the specified formal port in the design entity does not have the specified type, which is the type that the component's Component Declaration specifies for the actual port with the same name. The port names and types in the component's Component Declaration must match those in the design entity.
ACTION: Change the port in the design entity or Component Declaration so the ports have the same name and type, or remove the port from both the design entity and the Component Declaration.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.