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CAUSE: In an expression at the specified location in a VHDL Design File (.vhd), you attempted to specify an enable condition for a clock edge by merging two enable signals. However, Quartus Prime Integrated Synthesis cannot infer a register to implement the clock enable condition because you attempted to merge the two enable signals using the specified binary operator, which is not AND, OR, or XOR. You must combine the enable signals only with a binary AND, OR, or XOR.
PROCESS (clk) BEGIN -- Clock enable condition = (en1 AND en2) IF((rising_edge(clk) AND en1) AND (rising_edge (clk) AND en2) THEN q1 <= data; END IF; -- You can also specify the previous clock enable condition as -- IF(rising_edge(clk) AND (en1 AND en2)) THEN -- q1 <= data; -- END IF; -- Clock enable condition = (en1 XOR en2) IF((rising_edge(clk) AND en1) XOR (rising_edge(CLK) AND en2)) THEN q2 <= data; END IF; -- You can also specify the previous clock enable condition as -- IF(rising_edge(clk) AND (en1 XOR en2)) THEN -- q2 <= data; -- END IF; END PROCESS;
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