List of Messages |
CAUSE: In a Verilog Design File (.v), you used Verilog-2001 attribute syntax to specify a synthesis attribute. However, you also specified Conformal LEC as your EDA formal verification tool. The Quartus Prime software and Conformal LEC support a different Verilog-2001 attribute syntax. Conformal LEC requires the keyword synthesis, whereas the Quartus Prime software does not. As a result, Conformal LEC may report a formal verification mismatch between the synthesized netlist and your HDL.
ACTION: Embed the synthesis attribute or directive in a comment with an appropriate pragma trigger. Conformal LEC and the Quartus Prime software both recognize synthesis and synopsys as pragma triggers. You may also remove Conformal LEC as your EDA formal verification tool.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.