List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, you referred to a named event. Quartus Prime Integrated Synthesis does not support references to named events, and it can not safely ignore them during synthesis without potentially changing the functionality of your design.
ACTION: Remove the reference to the named event. If doing so changes the behavior of your design, express the functionality of the named event using synthesizable constructs.
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