List of Messages |
CAUSE: A Task Declaration in a Verilog Design File (.v) contains a recursive Task Enable Statement at the specified location. However, Quartus Prime Integrated Synthesis does not support recursive Task Enable Statements in Task Declarations.
ACTION: Rewrite the Task Declaration to remove the recursive Task Enable Statement.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.