List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, you declared a real variable data type. Although Verilog HDL supports real variable data types, this type is not supported in the Quartus Prime software.
ACTION: Change the data type of the variable to something other than real.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.