List of Messages |
CAUSE: In a Gate Instantiation at the specified location in a Verilog Design File (.v), you specify a pullup or pulldown source that drives more than one net in its terminal list. Although Verilog HDL supports pullup and pulldown sources driving multiple nets, the Quartus Prime software allows pullup and pulldown sources to drive only one net.
pullup my_pullup (a, b, c, d);you should replace it with the following syntax:
pullup my_pullup1 (a); pullup my_pullup2 (b); pullup my_pullup3 (c); pullup my_pullup4 (d);
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