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CAUSE: In a Verilog Design File (.v) at the specified location, you instantiated an array of Module Instantiations. Although arrays of Module Instantiations are supported in Verilog HDL, they are not supported in the Quartus Prime software.
module my_and(in_a, in_b, out); input in_a, in_b; output out; assign out = in_a & in_b; endmodule module my_and_array (in1, in2, out); input [7:0] in1, in2; output [7:0] out; my_and and_array[7:0] (in1, in2, out); endmoduleIf this design is rewritten with a Generate Statement, as shown in following sample design, the design will then compile successfully.
module my_and(in_a, in_b, out); input in_a, in_b; output out; assign out = in_a & in_b; endmodule module my_and_array (in1, in2,out); input [7:0] in1, in2; output [7:0] out; genvar i; generate for (i = 0; i<8; i=i+1) begin:my_label_for_each_bit my_and and_array(in1[i], in2[i], out[i]); end endgenerate endmodule
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