List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, you used the specified name in an expression. However, Quartus Prime Integrated Synthesis cannot match the name to a specific declaration in your design. You may be referring to an object outside the current hierarchy, a Verilog feature that Integrated Synthesis does not support. You may also be referring to an undeclared object, or you may simply have misspelled the object's name.
ACTION: If you are referring to an object outside the current hierarchy, you must restructure your design so that the object is accessible from a port on the current module or on an instance in the current module. Otherwise, declare the object, or check the spelling of the specified name.
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