List of Messages |
CAUSE: In a block comment in a Verilog Design File (.v) at the specified location, you used a beginning comment delimiter (slash and asterisk, or /*) without a corresponding ending comment delimiter (asterisk and slash, or */). As a result, Quartus Prime Integrated Synthesis unexpectedly reached the end-of-file marker and consequently disabled further processing of the file.
ACTION: Add a */ at the end of the comment block that begins with the unmatched /*.
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