List of Messages |
CAUSE: In a user-defined primitive (UDP) definition at the specified location in a Verilog Design File (.v), one of the lines of the UDP table definition is missing the colon character (:) that separates inputs from outputs.
ACTION: Insert a colon (:) between the inputs and outputs in the table.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.