List of Messages |
CAUSE: In a user-defined primitive (UDP) declaration at the specified location in a Verilog Design File (.v), you used a UDP table; however, the UDP table, which Quartus Prime Integrated Synthesis has identified as modeling combinational logic, has a table entry for modeling sequential logic.
ACTION: Change the UDP table to be either entirely combinational, or entirely sequential.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.