List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, you used a replication operation with a multiplier value that is not constant, for example, assign out = {myvar{in}} where myvar is a reg or integer. The multiplier value in a replication operation must be a constant so that the width of the expression can be computed during synthesis.
reg [1:0] in; integer i = 4; assign out = {i{in};
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.