List of Messages |
CAUSE: In a procedural assignment at the specified location in a Verilog Design File (.v), you assigned a value to the specified object, which was declared with a net data type (wire, wand, and so on) rather than with a variable data type (reg, integer, and so on). In Verilog HDL, you must use continuous assignments when targeting nets, and procedural assignments when targeting variables.
ACTION: Declare the specified object with a variable data type, if that is appropriate, or use a continuous assignment to assign a value to the object.
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