List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, you used a Defparam Statement or a named Module Instance Parameter Value Assignment list to change the value of a parameter in a module that you are instantiating. However, the specified parameter does not exist in the instantiated module. This error may occur if you have mistyped the parameter name.
ACTION: Carefully check the names in the Parameter Value Assignment Statement and in the instantiated module to make sure they match.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.