List of Messages |
CAUSE: In an expression at the specified location in a Verilog Design File (.v), you indexed the specified array. However, you specified more indices than there are accessible dimensions in the array.
ACTION: Remove extra index expressions from the indexed name, or declare the array object with more dimensions.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.