List of Messages |
CAUSE: In a Function Declaration at the specified location in a Verilog Design File (.v), you declared a function that has an output or inout port. However, Verilog HDL functions must have only input ports. You must not specify an output or inout port for a Verilog HDL function, because the function name itself is the name of the output port.
function my_and_func; input a; input b; begin my_and_func = a & b; end endfunction // my_funcTo use this function in a Verilog HDL module, you would use the following syntax:
assign out = my_func(in1, in2);
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