List of Messages |
CAUSE: In a Generate Statement at the specified location in a Verilog Design File (.v), you used one or more Function Declarations or Task Declarations in a generate loop. However, generate loops cannot contain Function or Task Declarations because a function or task cannot be declared multiple times. Instead, you can use Function or Task Declarations in generate conditionals.
ACTION: Remove the Function or Task Declarations from the generate loop, or change the generate loop to a generate conditional.
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