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reg q_pos, q_neg; always @ (posedge clk or negedge clk) begin if (clk == 1'b1) q_pos <= data; else q_neg <= data; endQuartus Prime Integrated Synthesis cannot infer both types of registers in the same construct, nor can it infer dual-edge triggered registers.
reg q_pos, q_neg; always @ (posedge clk) begin q_pos <= data; end always @ (negedge clk) begin q_neg <= data; end
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