List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, you declared the specified variable name, but the name is already defined elsewhere in the design. For example, you may have used the same name for a wire and for a module instantiation. All identifiers within a single module must have unique names.
ACTION: Choose a new name for the variable.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.