List of Messages |
CAUSE: In a Function Declaration at the specified location in the Verilog Design File (.v), you did not specify an input for the function you are declaring. However, a function must have at least one input.
ACTION: Because tasks do not require at least one input, you can convert the function to a task by replacing the Function Declaration with a Task Declaration. Or, specify at least one input for the function in the Function Declaration.
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