List of Messages |
CAUSE: In an Always Construct at the specified location in a Verilog Design File (.v), you used a Deassign Statement; however, although Verilog HDL supports Deassign Statements, which release registers from Procedural Continuous Assignments, they are not supported in the Quartus Prime software.
ACTION: Remove both the Procedural Continuous Assignment Statement and the Deassign Statement from the Always Construct and replace them with an If Statement that has appropriate condition expressions for specifying assignment conditions.
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