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ENTITY example IS PORT ( b1 : INOUT BIT; b2 : INOUT BIT ); END example; ARCHITECTURE a OF example IS BEGIN b2 <= b1; b1 <= b2; END a;
ACTION: If you do not require a bidirectional connection between the two ports, remove one of the assignments and redeclare the assigned port as an output. If you require a bidirectional connection, you will need to revise your design depending on your source language: In Verilog, you can use the tran primitive to create a bidirectional connection between the two ports. In VHDL, such a connection is effectively impossible, so you will need to rework your design to avoid it.
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