List of Messages |
CAUSE: You attempted to create a symbol/include/instantiation/component file for the specified entity in a VHDL Design File (.vhd). However, the specified port has a type that is not supported by the current release of symbol/include/instantiation/component file generator. For example, the port may have a record or unconstrained array type, or it may have a constrained array type with a complicated constraint. In general, the constraint must be defined by a constant expression, which may include references to objects (e.g. constants and functions) in packages, or by a range expression that is a simple arithmetic expression involving only generics and integer literals. Because the port has an unsupported type, the Quartus Prime software cannot create a symbol/include/instantiation/component file from the VHDL Design File.
ACTION: Omit the port from the entity, or change its type.
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