List of Messages |
CAUSE: You attempted to create a symbol/include/instantiation/component file for the specified module in a Verilog Design File (.vhd). However, the specified port on the module has a type that cannot be represented by a symbol/include/instantiation/component file. Unsupported port types include SystemVerilog structs, interfaces, or modports. Most array or vector types are generally supported, but the their bounds must be defined by constant expressions or by simple arithmetic expressions involving module parameters and integer literals. Because the specified port has an unsupported type, the Quartus Prime software cannot create a symbol/include/instantiation/component file for the module.
ACTION: Omit the port from the module declaration or change its type.
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