List of Messages |
CAUSE: In a function call or task enable at the specified location in a SystemVerilog Design File (.sv), you bound the specified output to an empty expression. This binding may be implicit if you did not specify an actual binding for the argument. Output arguments cannot be bound to empty expressions either implicitly or explicitly. They must be bound to expressions that are legal on the left-hand side of a sequential assignment.
ACTION: Specify a legal binding for the specified output argument.
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