List of Messages |
always_comb begin if(sel == 1'b1) o = a; else if(sel == 1'b0) o = b; endIntegrated Synthesis will infer a latch for o initially. Later on, during optimization, Integrated Synthesis will remove the latch as unnecessary. However, Altera advises against such descriptions. During simulation, o behaves as a latch when sel == 1'bx, which may result in a mismatch between the simulated behavior of the design and the synthesized netlist.
ACTION: If you intended to describe latched logic, then use an always_latch construct. Otherwise, if you intended to describe purely combinational logic, verify that you assign an updated value to every variable in all possible paths through the always construct. For false latches, you can add a default assignment at the beginning of the always construct to remove both the latch and this error.
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