List of Messages |
CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you used the specified value for the message_level synthesis directive. However, the specified value is not a legal value for this synthesis directive. Legal message_level values are Level1, Level2, Level3.
ACTION: Specify a legal value for the message_level synthesis directive.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.