List of Messages |
CAUSE: In an Entity Declaration at the specified location in a VHDL Design File (.vhd), you specified an unconstrained port. However, the ports in an Entity Declaration must be constrained.
ACTION: Make sure all the ports in the Entity Declaration are constrained by specifying sizes or ranges for the ports.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.