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PROCESS (clk1, clk2, reset) BEGIN IF (reset = '0') THEN Q1 <= '0'; Q2 <= '0'; ELSE IF (rising_edge(clk1)) THEN Q1 <= data1; ELSE IF (rising_edge(clk2)) THEN Q2 <= data2; END IF; END PROCESS;Because the statement tests for the clock edges of multiple clocks, the Quartus Prime software cannot synthesize logic for the statement.
PROCESS (clk1, clk2, reset) BEGIN IF (reset = '0') THEN q1 <= '0'; ELSE IF (rising_edge(clk1)) THEN q1 <= data1; END IF; IF (reset = '0') THEN q2 <= '0'; ELSE IF (rising_edge(clk2)) THEN q2 <= data2; END IF; END PROCESS;
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